Commit e0aba17a authored by schoko's avatar schoko
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="2.14.2" version="1.0">
This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution).
<lib desc="#Wiring" name="0"/>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2">
<tool name="Multiplexer">
<a name="enable" val="false"/>
</tool>
<tool name="Demultiplexer">
<a name="enable" val="false"/>
</tool>
</lib>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4">
<tool name="ROM">
<a name="contents">addr/data: 8 8
0
</a>
</tool>
</lib>
<lib desc="#I/O" name="5"/>
<lib desc="#HDL-IP" name="6">
<tool name="VHDL Entity">
<a name="content">--------------------------------------------------------------------------------
-- HEIG-VD, institute REDS, 1400 Yverdon-les-Bains
-- Project :
-- File :
-- Autor :
-- Date :
--
--------------------------------------------------------------------------------
-- Description :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
entity VHDL_Component is
port(
------------------------------------------------------------------------------
--Insert input ports below
horloge_i : in std_logic; -- input bit example
val_i : in std_logic_vector(3 downto 0); -- input vector example
------------------------------------------------------------------------------
--Insert output ports below
max_o : out std_logic; -- output bit example
cpt_o : out std_logic_Vector(3 downto 0) -- output vector example
);
end VHDL_Component;
--------------------------------------------------------------------------------
--Complete your VHDL description below
architecture type_architecture of VHDL_Component is
begin
end type_architecture;
</a>
</tool>
</lib>
<lib desc="#TCL" name="7">
<tool name="TclGeneric">
<a name="content">library ieee;
use ieee.std_logic_1164.all;
entity TCL_Generic is
port(
--Insert input ports below
horloge_i : in std_logic; -- input bit example
val_i : in std_logic_vector(3 downto 0); -- input vector example
--Insert output ports below
max_o : out std_logic; -- output bit example
cpt_o : out std_logic_Vector(3 downto 0) -- output vector example
);
end TCL_Generic;
</a>
</tool>
</lib>
<lib desc="#Base" name="8">
<tool name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
</lib>
<lib desc="#BFH-Praktika" name="9"/>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
<a name="tickmain" val="half_period"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Menu Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</tool>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
</toolbar>
<circuit name="main">
<a name="circuit" val="main"/>
<a name="clabel" val=""/>
<a name="clabelup" val="east"/>
<a name="clabelfont" val="SansSerif bold 16"/>
<a name="circuitnamedbox" val="true"/>
<a name="circuitvhdlpath" val=""/>
<wire from="(560,450)" to="(560,650)"/>
<wire from="(380,290)" to="(440,290)"/>
<wire from="(1160,790)" to="(1270,790)"/>
<wire from="(580,440)" to="(580,580)"/>
<wire from="(1340,450)" to="(1340,530)"/>
<wire from="(1340,530)" to="(1450,530)"/>
<wire from="(1200,400)" to="(1200,420)"/>
<wire from="(590,510)" to="(640,510)"/>
<wire from="(750,570)" to="(750,700)"/>
<wire from="(910,350)" to="(910,610)"/>
<wire from="(30,100)" to="(30,430)"/>
<wire from="(1220,420)" to="(1220,450)"/>
<wire from="(300,690)" to="(740,690)"/>
<wire from="(1120,180)" to="(1240,180)"/>
<wire from="(350,40)" to="(350,260)"/>
<wire from="(920,330)" to="(920,540)"/>
<wire from="(410,140)" to="(640,140)"/>
<wire from="(630,470)" to="(630,490)"/>
<wire from="(620,540)" to="(620,560)"/>
<wire from="(940,290)" to="(940,400)"/>
<wire from="(420,130)" to="(420,230)"/>
<wire from="(1010,80)" to="(1030,80)"/>
<wire from="(280,310)" to="(440,310)"/>
<wire from="(580,330)" to="(580,440)"/>
<wire from="(1330,490)" to="(1330,540)"/>
<wire from="(1100,220)" to="(1110,220)"/>
<wire from="(270,290)" to="(270,720)"/>
<wire from="(1060,490)" to="(1130,490)"/>
<wire from="(560,350)" to="(560,450)"/>
<wire from="(950,90)" to="(980,90)"/>
<wire from="(1170,130)" to="(1170,190)"/>
<wire from="(290,330)" to="(440,330)"/>
<wire from="(930,310)" to="(930,470)"/>
<wire from="(30,100)" to="(430,100)"/>
<wire from="(300,350)" to="(440,350)"/>
<wire from="(1200,230)" to="(1360,230)"/>
<wire from="(270,290)" to="(350,290)"/>
<wire from="(990,540)" to="(1060,540)"/>
<wire from="(1330,470)" to="(1360,470)"/>
<wire from="(1340,450)" to="(1360,450)"/>
<wire from="(680,500)" to="(760,500)"/>
<wire from="(1030,30)" to="(1030,80)"/>
<wire from="(430,100)" to="(430,220)"/>
<wire from="(1450,490)" to="(1450,530)"/>
<wire from="(1220,450)" to="(1240,450)"/>
<wire from="(700,30)" to="(700,40)"/>
<wire from="(1220,420)" to="(1330,420)"/>
<wire from="(560,290)" to="(610,290)"/>
<wire from="(1450,420)" to="(1450,450)"/>
<wire from="(870,310)" to="(930,310)"/>
<wire from="(580,580)" to="(640,580)"/>
<wire from="(1110,360)" to="(1210,360)"/>
<wire from="(440,190)" to="(560,190)"/>
<wire from="(680,640)" to="(740,640)"/>
<wire from="(350,280)" to="(350,290)"/>
<wire from="(640,140)" to="(680,140)"/>
<wire from="(380,270)" to="(380,290)"/>
<wire from="(1050,300)" to="(1240,300)"/>
<wire from="(1120,170)" to="(1310,170)"/>
<wire from="(660,590)" to="(660,620)"/>
<wire from="(280,310)" to="(280,710)"/>
<wire from="(500,420)" to="(610,420)"/>
<wire from="(1240,400)" to="(1300,400)"/>
<wire from="(950,210)" to="(990,210)"/>
<wire from="(760,500)" to="(760,710)"/>
<wire from="(590,430)" to="(590,510)"/>
<wire from="(630,400)" to="(630,420)"/>
<wire from="(630,470)" to="(930,470)"/>
<wire from="(620,540)" to="(920,540)"/>
<wire from="(610,420)" to="(610,440)"/>
<wire from="(580,330)" to="(750,330)"/>
<wire from="(1240,130)" to="(1240,180)"/>
<wire from="(1240,490)" to="(1240,540)"/>
<wire from="(1040,370)" to="(1190,370)"/>
<wire from="(1330,420)" to="(1330,470)"/>
<wire from="(1050,260)" to="(1060,260)"/>
<wire from="(30,430)" to="(30,790)"/>
<wire from="(590,310)" to="(750,310)"/>
<wire from="(560,310)" to="(590,310)"/>
<wire from="(610,440)" to="(640,440)"/>
<wire from="(590,310)" to="(590,430)"/>
<wire from="(1240,540)" to="(1330,540)"/>
<wire from="(290,330)" to="(290,700)"/>
<wire from="(1420,450)" to="(1450,450)"/>
<wire from="(1420,490)" to="(1450,490)"/>
<wire from="(1050,260)" to="(1050,300)"/>
<wire from="(1030,90)" to="(1360,90)"/>
<wire from="(640,90)" to="(640,140)"/>
<wire from="(1110,470)" to="(1130,470)"/>
<wire from="(1150,230)" to="(1170,230)"/>
<wire from="(870,330)" to="(920,330)"/>
<wire from="(1100,200)" to="(1100,220)"/>
<wire from="(1110,450)" to="(1110,470)"/>
<wire from="(1030,90)" to="(1030,100)"/>
<wire from="(560,220)" to="(750,220)"/>
<wire from="(380,450)" to="(560,450)"/>
<wire from="(1110,360)" to="(1110,450)"/>
<wire from="(610,290)" to="(610,420)"/>
<wire from="(710,40)" to="(710,130)"/>
<wire from="(300,350)" to="(300,690)"/>
<wire from="(500,400)" to="(500,420)"/>
<wire from="(660,520)" to="(660,550)"/>
<wire from="(460,400)" to="(460,430)"/>
<wire from="(1270,790)" to="(1390,790)"/>
<wire from="(1300,400)" to="(1300,450)"/>
<wire from="(30,430)" to="(60,430)"/>
<wire from="(1040,250)" to="(1060,250)"/>
<wire from="(1010,100)" to="(1030,100)"/>
<wire from="(410,250)" to="(440,250)"/>
<wire from="(560,330)" to="(580,330)"/>
<wire from="(620,630)" to="(640,630)"/>
<wire from="(410,140)" to="(410,250)"/>
<wire from="(770,430)" to="(770,720)"/>
<wire from="(420,230)" to="(440,230)"/>
<wire from="(680,430)" to="(770,430)"/>
<wire from="(420,400)" to="(420,440)"/>
<wire from="(680,250)" to="(750,250)"/>
<wire from="(680,570)" to="(750,570)"/>
<wire from="(1080,240)" to="(1110,240)"/>
<wire from="(1160,500)" to="(1160,790)"/>
<wire from="(340,40)" to="(350,40)"/>
<wire from="(1330,490)" to="(1360,490)"/>
<wire from="(380,400)" to="(380,450)"/>
<wire from="(1040,250)" to="(1040,370)"/>
<wire from="(740,640)" to="(740,690)"/>
<wire from="(1310,130)" to="(1310,170)"/>
<wire from="(700,40)" to="(710,40)"/>
<wire from="(1220,470)" to="(1240,470)"/>
<wire from="(630,490)" to="(640,490)"/>
<wire from="(1190,370)" to="(1190,450)"/>
<wire from="(630,400)" to="(940,400)"/>
<wire from="(640,90)" to="(950,90)"/>
<wire from="(990,210)" to="(990,540)"/>
<wire from="(1220,450)" to="(1220,470)"/>
<wire from="(1060,270)" to="(1060,420)"/>
<wire from="(270,720)" to="(770,720)"/>
<wire from="(560,350)" to="(750,350)"/>
<wire from="(710,230)" to="(750,230)"/>
<wire from="(660,450)" to="(660,480)"/>
<wire from="(870,350)" to="(910,350)"/>
<wire from="(560,190)" to="(560,220)"/>
<wire from="(620,610)" to="(910,610)"/>
<wire from="(30,790)" to="(1160,790)"/>
<wire from="(420,130)" to="(710,130)"/>
<wire from="(440,190)" to="(440,220)"/>
<wire from="(1210,360)" to="(1210,370)"/>
<wire from="(1360,90)" to="(1360,230)"/>
<wire from="(860,30)" to="(1030,30)"/>
<wire from="(1330,420)" to="(1450,420)"/>
<wire from="(1060,540)" to="(1240,540)"/>
<wire from="(620,610)" to="(620,630)"/>
<wire from="(1120,190)" to="(1170,190)"/>
<wire from="(1060,490)" to="(1060,540)"/>
<wire from="(680,140)" to="(680,250)"/>
<wire from="(280,710)" to="(760,710)"/>
<wire from="(1060,420)" to="(1200,420)"/>
<wire from="(620,560)" to="(640,560)"/>
<wire from="(420,440)" to="(580,440)"/>
<wire from="(710,130)" to="(710,230)"/>
<wire from="(430,220)" to="(440,220)"/>
<wire from="(290,700)" to="(750,700)"/>
<wire from="(1270,500)" to="(1270,790)"/>
<wire from="(1240,300)" to="(1240,400)"/>
<wire from="(950,90)" to="(950,210)"/>
<wire from="(870,290)" to="(940,290)"/>
<wire from="(1390,500)" to="(1390,790)"/>
<wire from="(560,650)" to="(640,650)"/>
<wire from="(460,430)" to="(590,430)"/>
<wire from="(610,290)" to="(750,290)"/>
<wire from="(1110,450)" to="(1130,450)"/>
<wire from="(1200,420)" to="(1220,420)"/>
<wire from="(1220,400)" to="(1240,400)"/>
<wire from="(630,420)" to="(640,420)"/>
<comp lib="5" loc="(500,400)" name="LED">
<a name="facing" val="east"/>
<a name="color" val="#2328f0"/>
</comp>
<comp lib="5" loc="(420,400)" name="LED">
<a name="facing" val="east"/>
<a name="color" val="#2335f0"/>
</comp>
<comp lib="4" loc="(750,200)" name="Shift Register">
<a name="length" val="4"/>
</comp>
<comp lib="5" loc="(380,400)" name="LED">
<a name="facing" val="east"/>
<a name="color" val="#2233f0"/>
</comp>
<comp lib="3" loc="(680,500)" name="Adder">
<a name="width" val="1"/>
</comp>
<comp lib="4" loc="(1140,440)" name="J-K Flip-Flop"/>
<comp lib="0" loc="(340,40)" name="Pin"/>
<comp lib="3" loc="(680,640)" name="Adder">
<a name="width" val="1"/>
</comp>
<comp lib="0" loc="(1170,130)" name="Pin"/>
<comp lib="4" loc="(1250,440)" name="J-K Flip-Flop"/>
<comp lib="4" loc="(1370,440)" name="J-K Flip-Flop"/>
<comp lib="5" loc="(60,430)" name="Button">
<a name="facing" val="west"/>
<a name="label" val="Reset"/>
<a name="labelloc" val="east"/>
</comp>
<comp lib="0" loc="(1240,130)" name="Pin"/>
<comp lib="3" loc="(1150,230)" name="Comparator">
<a name="width" val="3"/>
</comp>
<comp lib="0" loc="(1080,240)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="3"/>
<a name="incoming" val="3"/>
<a name="bit0" val="2"/>
<a name="bit2" val="0"/>
</comp>
<comp lib="1" loc="(980,90)" name="AND Gate">
<a name="facing" val="west"/>
<a name="size" val="30"/>
</comp>
<comp lib="1" loc="(1200,230)" name="NOT Gate"/>
<comp lib="5" loc="(460,400)" name="LED">
<a name="facing" val="east"/>
<a name="color" val="#2325f0"/>
</comp>
<comp lib="1" loc="(1210,370)" name="AND Gate">
<a name="facing" val="north"/>
<a name="size" val="30"/>
</comp>
<comp lib="0" loc="(860,30)" name="Clock">
<a name="label" val="Takt"/>
</comp>
<comp lib="0" loc="(1100,200)" name="Splitter">
<a name="fanout" val="3"/>
<a name="incoming" val="3"/>
</comp>
<comp lib="3" loc="(680,570)" name="Adder">
<a name="width" val="1"/>
</comp>
<comp lib="0" loc="(1310,130)" name="Pin"/>
<comp lib="0" loc="(700,30)" name="Constant">
<a name="facing" val="west"/>
</comp>
<comp lib="4" loc="(440,200)" name="Shift Register">
<a name="length" val="4"/>
</comp>
<comp lib="3" loc="(680,430)" name="Adder">
<a name="width" val="1"/>
</comp>
<comp lib="1" loc="(380,270)" name="OR Gate">
<a name="size" val="30"/>
</comp>
</circuit>
</project>
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="2.14.2" version="1.0">
This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution).
<lib desc="#Wiring" name="0">
<tool name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
<a name="appear" val="center"/>
</tool>
<tool name="Pin">
<a name="facing" val="north"/>
</tool>
<tool name="Probe">
<a name="facing" val="north"/>
</tool>
<tool name="Clock">
<a name="facing" val="north"/>
</tool>
<tool name="Constant">
<a name="facing" val="west"/>
<a name="value" val="0x0"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2">
<tool name="Multiplexer">
<a name="enable" val="false"/>
</tool>
<tool name="Demultiplexer">
<a name="enable" val="false"/>
</tool>
</lib>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4">
<tool name="ROM">
<a name="contents">addr/data: 8 8
0
</a>
</tool>
</lib>
<lib desc="#I/O" name="5"/>
<lib desc="#HDL-IP" name="6">
<tool name="VHDL Entity">
<a name="content">--------------------------------------------------------------------------------
-- HEIG-VD, institute REDS, 1400 Yverdon-les-Bains
-- Project :
-- File :
-- Autor :
-- Date :
--
--------------------------------------------------------------------------------
-- Description :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
entity VHDL_Component is
port(
------------------------------------------------------------------------------
--Insert input ports below
horloge_i : in std_logic; -- input bit example
val_i : in std_logic_vector(3 downto 0); -- input vector example
------------------------------------------------------------------------------
--Insert output ports below
max_o : out std_logic; -- output bit example
cpt_o : out std_logic_Vector(3 downto 0) -- output vector example
);
end VHDL_Component;
--------------------------------------------------------------------------------
--Complete your VHDL description below
architecture type_architecture of VHDL_Component is
begin
end type_architecture;
</a>
</tool>
</lib>
<lib desc="#TCL" name="7">
<tool name="TclGeneric">
<a name="content">library ieee;
use ieee.std_logic_1164.all;
entity TCL_Generic is
port(
--Insert input ports below
horloge_i : in std_logic; -- input bit example
val_i : in std_logic_vector(3 downto 0); -- input vector example
--Insert output ports below
max_o : out std_logic; -- output bit example
cpt_o : out std_logic_Vector(3 downto 0) -- output vector example
);
end TCL_Generic;
</a>
</tool>
</lib>
<lib desc="#Base" name="8">
<tool name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="left"/>
<a name="valign" val="base"/>
</tool>
</lib>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="file#logi7400/logi7400.circ" name="10"/>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
<a name="tickmain" val="half_period"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Menu Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="left"/>
<a name="valign" val="base"/>
</tool>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</tool>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
</toolbar>
<circuit name="main">
<a name="circuit" val="main"/>
<a name="clabel" val="Ram"/>
<a name="clabelup" val="east"/>
<a name="clabelfont" val="SansSerif bold 16"/>
<a name="circuitnamedbox" val="true"/>
<a name="circuitvhdlpath" val=""/>
<wire from="(1320,80)" to="(1320,100)"/>
<wire from="(1130,80)" to="(1130,160)"/>
<wire from="(420,250)" to="(480,250)"/>
<wire from="(760,280)" to="(810,280)"/>
<wire from="(830,140)" to="(890,140)"/>
<wire from="(810,400)" to="(1060,400)"/>
<wire from="(60,420)" to="(60,430)"/>
<wire from="(1140,230)" to="(1140,450)"/>
<wire from="(760,470)" to="(820,470)"/>
<wire from="(840,490)" to="(840,710)"/>
<wire from="(840,720)" to="(840,750)"/>
<wire from="(170,690)" to="(170,710)"/>
<wire from="(380,420)" to="(480,420)"/>
<wire from="(1110,550)" to="(1110,560)"/>
<wire from="(790,780)" to="(790,860)"/>
<wire from="(830,300)" to="(830,380)"/>
<wire from="(990,460)" to="(1100,460)"/>
<wire from="(1090,450)" to="(1140,450)"/>
<wire from="(1100,460)" to="(1150,460)"/>
<wire from="(1110,470)" to="(1160,470)"/>
<wire from="(1120,480)" to="(1170,480)"/>
<wire from="(840,710)" to="(860,710)"/>
<wire from="(1030,300)" to="(1050,300)"/>
<wire from="(1120,480)" to="(1120,530)"/>
<wire from="(1160,160)" to="(1160,210)"/>
<wire from="(830,380)" to="(830,480)"/>
<wire from="(820,290)" to="(820,390)"/>
<wire from="(440,390)" to="(460,390)"/>
<wire from="(1050,480)" to="(1120,480)"/>
<wire from="(940,560)" to="(970,560)"/>
<wire from="(1110,470)" to="(1110,530)"/>
<wire from="(980,160)" to="(980,320)"/>
<wire from="(850,830)" to="(880,830)"/>
<wire from="(380,240)" to="(380,420)"/>
<wire from="(370,230)" to="(370,410)"/>
<wire from="(810,280)" to="(810,400)"/>
<wire from="(420,430)" to="(420,670)"/>
<wire from="(810,460)" to="(810,710)"/>
<wire from="(820,130)" to="(890,130)"/>
<wire from="(320,200)" to="(320,260)"/>
<wire from="(840,370)" to="(980,370)"/>
<wire from="(330,210)" to="(330,270)"/>
<wire from="(340,220)" to="(340,280)"/>
<wire from="(320,260)" to="(450,260)"/>
<wire from="(830,480)" to="(830,720)"/>
<wire from="(730,450)" to="(740,450)"/>
<wire from="(440,270)" to="(440,390)"/>
<wire from="(1060,290)" to="(1060,400)"/>
<wire from="(920,450)" to="(970,450)"/>
<wire from="(1090,450)" to="(1090,530)"/>
<wire from="(940,550)" to="(940,560)"/>
<wire from="(420,290)" to="(420,430)"/>
<wire from="(300,290)" to="(420,290)"/>
<wire from="(1000,690)" to="(1190,690)"/>
<wire from="(950,480)" to="(1050,480)"/>
<wire from="(820,470)" to="(820,750)"/>
<wire from="(1100,460)" to="(1100,530)"/>
<wire from="(370,410)" to="(480,410)"/>
<wire from="(830,380)" to="(1000,380)"/>
<wire from="(980,350)" to="(980,370)"/>
<wire from="(300,280)" to="(340,280)"/>
<wire from="(230,780)" to="(780,780)"/>
<wire from="(990,350)" to="(990,460)"/>
<wire from="(40,670)" to="(70,670)"/>
<wire from="(340,280)" to="(430,280)"/>
<wire from="(70,670)" to="(420,670)"/>
<wire from="(860,710)" to="(860,750)"/>
<wire from="(1020,350)" to="(1020,390)"/>
<wire from="(300,260)" to="(320,260)"/>
<wire from="(1170,230)" to="(1170,480)"/>
<wire from="(820,130)" to="(820,290)"/>
<wire from="(830,140)" to="(830,300)"/>
<wire from="(840,150)" to="(840,310)"/>
<wire from="(810,120)" to="(810,280)"/>
<wire from="(120,480)" to="(140,480)"/>
<wire from="(1010,160)" to="(1010,320)"/>
<wire from="(810,780)" to="(810,840)"/>
<wire from="(450,380)" to="(460,380)"/>
<wire from="(480,250)" to="(490,250)"/>
<wire from="(760,480)" to="(830,480)"/>
<wire from="(1030,100)" to="(1160,100)"/>
<wire from="(270,280)" to="(280,280)"/>