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Commit b58e9d42 authored by schoko's avatar schoko
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alu.circ 0 → 100644
View file @ b58e9d42
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="2.14.2" version="1.0">
This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution).
<lib desc="#Wiring" name="0">
<tool name="Splitter">
<a name="facing" val="south"/>
<a name="appear" val="center"/>
</tool>
<tool name="Pin">
<a name="facing" val="north"/>
</tool>
<tool name="Probe">
<a name="facing" val="north"/>
</tool>
<tool name="Pull Resistor">
<a name="facing" val="north"/>
</tool>
<tool name="Clock">
<a name="facing" val="north"/>
</tool>
<tool name="Constant">
<a name="facing" val="west"/>
<a name="value" val="0x0"/>
</tool>
</lib>
<lib desc="#Gates" name="1">
<tool name="Buffer">
<a name="facing" val="south"/>
</tool>
</lib>
<lib desc="#Plexers" name="2">
<tool name="Multiplexer">
<a name="enable" val="false"/>
</tool>
<tool name="Demultiplexer">
<a name="enable" val="false"/>
</tool>
</lib>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4">
<tool name="ROM">
<a name="contents">addr/data: 8 8
0
</a>
</tool>
</lib>
<lib desc="#I/O" name="5"/>
<lib desc="#HDL-IP" name="6">
<tool name="VHDL Entity">
<a name="content">--------------------------------------------------------------------------------
-- HEIG-VD, institute REDS, 1400 Yverdon-les-Bains
-- Project :
-- File :
-- Autor :
-- Date :
--
--------------------------------------------------------------------------------
-- Description :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
entity VHDL_Component is
port(
------------------------------------------------------------------------------
--Insert input ports below
horloge_i : in std_logic; -- input bit example
val_i : in std_logic_vector(3 downto 0); -- input vector example
------------------------------------------------------------------------------
--Insert output ports below
max_o : out std_logic; -- output bit example
cpt_o : out std_logic_Vector(3 downto 0) -- output vector example
);
end VHDL_Component;
--------------------------------------------------------------------------------
--Complete your VHDL description below
architecture type_architecture of VHDL_Component is
begin
end type_architecture;
</a>
</tool>
</lib>
<lib desc="#TCL" name="7">
<tool name="TclGeneric">
<a name="content">library ieee;
use ieee.std_logic_1164.all;
entity TCL_Generic is
port(
--Insert input ports below
horloge_i : in std_logic; -- input bit example
val_i : in std_logic_vector(3 downto 0); -- input vector example
--Insert output ports below
max_o : out std_logic; -- output bit example
cpt_o : out std_logic_Vector(3 downto 0) -- output vector example
);
end TCL_Generic;
</a>
</tool>
</lib>
<lib desc="#Base" name="8">
<tool name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
</lib>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="file#logi7400/logi7400.circ" name="10"/>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
<a name="tickmain" val="half_period"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Menu Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</tool>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
</toolbar>
<circuit name="main">
<a name="circuit" val="main"/>
<a name="clabel" val=""/>
<a name="clabelup" val="east"/>
<a name="clabelfont" val="SansSerif bold 16"/>
<a name="circuitnamedbox" val="true"/>
<a name="circuitvhdlpath" val=""/>
<wire from="(430,280)" to="(490,280)"/>
<wire from="(620,300)" to="(620,310)"/>
<wire from="(400,240)" to="(450,240)"/>
<wire from="(270,180)" to="(450,180)"/>
<wire from="(440,150)" to="(620,150)"/>
<wire from="(430,410)" to="(430,420)"/>
<wire from="(390,410)" to="(390,420)"/>
<wire from="(330,230)" to="(450,230)"/>
<wire from="(490,270)" to="(490,280)"/>
<wire from="(480,200)" to="(600,200)"/>
<wire from="(590,220)" to="(590,290)"/>
<wire from="(230,160)" to="(270,160)"/>
<wire from="(310,220)" to="(310,320)"/>
<wire from="(540,420)" to="(540,460)"/>
<wire from="(530,230)" to="(530,400)"/>
<wire from="(420,260)" to="(450,260)"/>
<wire from="(690,80)" to="(690,190)"/>
<wire from="(620,290)" to="(640,290)"/>
<wire from="(290,320)" to="(310,320)"/>
<wire from="(480,190)" to="(690,190)"/>
<wire from="(430,400)" to="(450,400)"/>
<wire from="(410,250)" to="(410,420)"/>
<wire from="(240,210)" to="(450,210)"/>
<wire from="(700,110)" to="(700,210)"/>
<wire from="(680,70)" to="(680,170)"/>
<wire from="(230,180)" to="(250,180)"/>
<wire from="(440,160)" to="(450,160)"/>
<wire from="(390,410)" to="(400,410)"/>
<wire from="(310,220)" to="(450,220)"/>
<wire from="(610,180)" to="(610,300)"/>
<wire from="(510,450)" to="(520,450)"/>
<wire from="(520,240)" to="(520,420)"/>
<wire from="(560,400)" to="(560,460)"/>
<wire from="(480,180)" to="(610,180)"/>
<wire from="(420,260)" to="(420,320)"/>
<wire from="(250,190)" to="(450,190)"/>
<wire from="(660,80)" to="(670,80)"/>
<wire from="(430,280)" to="(430,400)"/>
<wire from="(700,70)" to="(700,80)"/>
<wire from="(720,70)" to="(720,80)"/>
<wire from="(660,70)" to="(660,80)"/>
<wire from="(400,340)" to="(400,410)"/>
<wire from="(420,340)" to="(420,410)"/>
<wire from="(520,450)" to="(520,460)"/>
<wire from="(620,150)" to="(620,290)"/>
<wire from="(250,180)" to="(250,190)"/>
<wire from="(240,210)" to="(240,220)"/>
<wire from="(480,230)" to="(530,230)"/>
<wire from="(440,150)" to="(440,160)"/>
<wire from="(510,250)" to="(510,450)"/>
<wire from="(500,260)" to="(500,460)"/>
<wire from="(270,160)" to="(270,180)"/>
<wire from="(450,400)" to="(450,420)"/>
<wire from="(710,80)" to="(710,110)"/>
<wire from="(480,220)" to="(590,220)"/>
<wire from="(430,140)" to="(670,140)"/>
<wire from="(400,240)" to="(400,320)"/>
<wire from="(430,140)" to="(430,170)"/>
<wire from="(580,290)" to="(580,310)"/>
<wire from="(640,290)" to="(640,310)"/>
<wire from="(410,250)" to="(450,250)"/>
<wire from="(480,240)" to="(520,240)"/>
<wire from="(480,210)" to="(700,210)"/>
<wire from="(520,420)" to="(540,420)"/>
<wire from="(480,250)" to="(510,250)"/>
<wire from="(230,200)" to="(450,200)"/>
<wire from="(600,200)" to="(600,310)"/>
<wire from="(430,170)" to="(450,170)"/>
<wire from="(530,400)" to="(560,400)"/>
<wire from="(480,260)" to="(500,260)"/>
<wire from="(420,410)" to="(430,410)"/>
<wire from="(480,270)" to="(490,270)"/>
<wire from="(320,350)" to="(330,350)"/>
<wire from="(230,220)" to="(240,220)"/>
<wire from="(670,80)" to="(670,140)"/>
<wire from="(700,110)" to="(710,110)"/>
<wire from="(690,80)" to="(700,80)"/>
<wire from="(710,80)" to="(720,80)"/>
<wire from="(330,230)" to="(330,350)"/>
<wire from="(580,290)" to="(590,290)"/>
<wire from="(480,170)" to="(680,170)"/>
<wire from="(610,300)" to="(620,300)"/>
<comp lib="0" loc="(660,70)" name="Pin">
<a name="facing" val="south"/>
<a name="label" val="A1"/>
<a name="labelloc" val="north"/>
</comp>
<comp lib="10" loc="(480,160)" name="DIP_74181"/>
<comp lib="0" loc="(700,70)" name="Pin">
<a name="facing" val="south"/>
<a name="label" val="A3"/>
<a name="labelloc" val="north"/>
</comp>
<comp lib="0" loc="(580,310)" name="Pin">
<a name="facing" val="north"/>
<a name="label" val="B4"/>
<a name="labelloc" val="south"/>
</comp>
<comp lib="0" loc="(680,70)" name="Pin">
<a name="facing" val="south"/>
<a name="label" val="A2"/>
<a name="labelloc" val="north"/>
</comp>
<comp lib="0" loc="(500,460)" name="Pin">
<a name="facing" val="north"/>
</comp>
<comp lib="0" loc="(230,200)" name="Pin">
<a name="label" val="S2"/>
</comp>
<comp lib="0" loc="(720,70)" name="Pin">
<a name="facing" val="south"/>
<a name="label" val="A4"/>
<a name="labelloc" val="north"/>
</comp>
<comp lib="1" loc="(400,340)" name="NOT Gate">
<a name="facing" val="south"/>
<a name="size" val="20"/>
</comp>
<comp lib="0" loc="(320,350)" name="Pin">
<a name="label" val="M"/>
</comp>
<comp lib="0" loc="(230,160)" name="Pin">
<a name="label" val="S4"/>
</comp>
<comp lib="1" loc="(420,340)" name="NOT Gate">
<a name="facing" val="south"/>
<a name="size" val="20"/>
</comp>
<comp lib="5" loc="(430,420)" name="LED">
<a name="facing" val="north"/>
<a name="label" val="Y3"/>
<a name="labelloc" val="south"/>
</comp>
<comp lib="5" loc="(390,420)" name="LED">
<a name="facing" val="north"/>
<a name="label" val="Y1"/>
<a name="labelloc" val="south"/>
</comp>
<comp lib="0" loc="(230,180)" name="Pin">
<a name="label" val="S3"/>
</comp>
<comp lib="0" loc="(540,460)" name="Pin">
<a name="facing" val="north"/>
</comp>
<comp lib="5" loc="(410,420)" name="LED">
<a name="facing" val="north"/>
<a name="label" val="Y2"/>
<a name="labelloc" val="south"/>
</comp>
<comp lib="0" loc="(230,220)" name="Pin">
<a name="label" val="S1"/>
</comp>
<comp lib="5" loc="(450,420)" name="LED">
<a name="facing" val="north"/>
<a name="label" val="Y4"/>
<a name="labelloc" val="south"/>
</comp>
<comp lib="0" loc="(600,310)" name="Pin">
<a name="facing" val="north"/>
<a name="label" val="B3"/>
<a name="labelloc" val="south"/>
</comp>
<comp lib="0" loc="(640,310)" name="Pin">
<a name="facing" val="north"/>
<a name="label" val="B1"/>
<a name="labelloc" val="south"/>
</comp>
<comp lib="0" loc="(290,320)" name="Pin">
<a name="label" val="CIN"/>
</comp>
<comp lib="0" loc="(620,310)" name="Pin">
<a name="facing" val="north"/>
<a name="label" val="B2"/>
<a name="labelloc" val="south"/>
</comp>
</circuit>
</project>
v3.circ 0 → 100644
View file @ b58e9d42
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