Commit 2b67a06d authored by Alexander Krause's avatar Alexander Krause
Browse files

ram vorschaltung

parent ab74904f
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="2.14.2" version="1.0">
This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution).
<lib desc="#Wiring" name="0"/>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2">
<tool name="Multiplexer">
<a name="enable" val="false"/>
</tool>
<tool name="Demultiplexer">
<a name="enable" val="false"/>
</tool>
</lib>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4">
<tool name="ROM">
<a name="contents">addr/data: 8 8
0
</a>
</tool>
</lib>
<lib desc="#I/O" name="5"/>
<lib desc="#HDL-IP" name="6">
<tool name="VHDL Entity">
<a name="content">--------------------------------------------------------------------------------
-- HEIG-VD, institute REDS, 1400 Yverdon-les-Bains
-- Project :
-- File :
-- Autor :
-- Date :
--
--------------------------------------------------------------------------------
-- Description :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
entity VHDL_Component is
port(
------------------------------------------------------------------------------
--Insert input ports below
horloge_i : in std_logic; -- input bit example
val_i : in std_logic_vector(3 downto 0); -- input vector example
------------------------------------------------------------------------------
--Insert output ports below
max_o : out std_logic; -- output bit example
cpt_o : out std_logic_Vector(3 downto 0) -- output vector example
);
end VHDL_Component;
--------------------------------------------------------------------------------
--Complete your VHDL description below
architecture type_architecture of VHDL_Component is
begin
end type_architecture;
</a>
</tool>
</lib>
<lib desc="#TCL" name="7">
<tool name="TclGeneric">
<a name="content">library ieee;
use ieee.std_logic_1164.all;
entity TCL_Generic is
port(
--Insert input ports below
horloge_i : in std_logic; -- input bit example
val_i : in std_logic_vector(3 downto 0); -- input vector example
--Insert output ports below
max_o : out std_logic; -- output bit example
cpt_o : out std_logic_Vector(3 downto 0) -- output vector example
);
end TCL_Generic;
</a>
</tool>
</lib>
<lib desc="#Base" name="8">
<tool name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
</lib>
<lib desc="#BFH-Praktika" name="9"/>
<main name="ram_vorschaltung"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
<a name="tickmain" val="half_period"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Menu Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</tool>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
</toolbar>
<circuit name="ram_vorschaltung">
<a name="circuit" val="ram_vorschaltung"/>
<a name="clabel" val=""/>
<a name="clabelup" val="east"/>
<a name="clabelfont" val="SansSerif bold 16"/>
<a name="circuitnamedbox" val="true"/>
<a name="circuitvhdlpath" val=""/>
<appear>
<rect height="2" stroke="none" width="14" x="50" y="60"/>
<text fill="#404040" font-family="Dialog" font-size="12" text-anchor="end" x="83" y="68">CS</text>
<rect height="3" stroke="none" width="10" x="120" y="79"/>
<text fill="#404040" font-family="Dialog" font-size="12" text-anchor="end" x="115" y="84">WE_O</text>
<rect height="3" stroke="none" width="10" x="51" y="99"/>
<text fill="#404040" font-family="Dialog" font-size="12" text-anchor="end" x="83" y="106">WE</text>
<rect height="3" stroke="none" width="10" x="120" y="119"/>
<text fill="#404040" font-family="Dialog" font-size="12" text-anchor="end" x="115" y="124">OE_O</text>
<rect height="3" stroke="none" width="10" x="50" y="138"/>
<circ-port height="10" pin="380,430" width="10" x="45" y="135"/>
<circ-port height="10" pin="630,420" width="10" x="125" y="115"/>
<circ-port height="10" pin="380,370" width="10" x="45" y="95"/>
<circ-port height="10" pin="630,360" width="10" x="125" y="75"/>
<circ-port height="10" pin="380,320" width="10" x="45" y="55"/>
<text fill="#404040" font-family="Dialog" font-size="12" text-anchor="end" x="81" y="145">OE</text>
<rect height="20" stroke="none" width="60" x="63" y="153"/>
<rect fill="none" height="120" stroke="#000000" stroke-width="2" width="60" x="60" y="50"/>
<text fill="#ffffff" font-family="SansSerif" font-size="12" text-anchor="middle" x="90" y="165">ram vor</text>
<circ-anchor facing="east" height="6" width="6" x="47" y="57"/>
</appear>
<wire from="(620,420)" to="(620,430)"/>
<wire from="(620,350)" to="(620,360)"/>
<wire from="(420,450)" to="(470,450)"/>
<wire from="(460,320)" to="(480,320)"/>
<wire from="(480,320)" to="(480,330)"/>
<wire from="(530,350)" to="(620,350)"/>
<wire from="(460,410)" to="(470,410)"/>
<wire from="(420,430)" to="(420,450)"/>
<wire from="(520,430)" to="(620,430)"/>
<wire from="(380,320)" to="(460,320)"/>
<wire from="(380,370)" to="(480,370)"/>
<wire from="(460,320)" to="(460,410)"/>
<wire from="(380,430)" to="(420,430)"/>
<wire from="(620,420)" to="(630,420)"/>
<wire from="(620,360)" to="(630,360)"/>
<comp lib="0" loc="(380,430)" name="Pin">
<a name="output" val="true"/>
<a name="label" val="OE"/>
<a name="labelloc" val="east"/>
</comp>
<comp lib="0" loc="(380,370)" name="Pin">
<a name="output" val="true"/>
<a name="label" val="WE"/>
<a name="labelloc" val="east"/>
</comp>
<comp lib="1" loc="(530,350)" name="OR Gate"/>
<comp lib="0" loc="(380,320)" name="Pin">
<a name="output" val="true"/>
<a name="label" val="CS"/>
<a name="labelloc" val="east"/>
</comp>
<comp lib="0" loc="(630,420)" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="label" val="OE_O"/>
<a name="labelloc" val="east"/>
</comp>
<comp lib="1" loc="(520,430)" name="OR Gate"/>
<comp lib="0" loc="(630,360)" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="label" val="WE_O"/>
<a name="labelloc" val="east"/>
</comp>
</circuit>
</project>
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